The present invention relates to a multilayer wiring board fabricating method and multilayer wiring board fabricated with use of the method. More particularly, it concerns a high-density, highly reliable multilayer wiring board and a multitip module board for use in a main frame computer, a workstation, a multimedia computer, and an ATM exchanger for communication and their fabricating method.
Hitherto multilayer wiring boards for use in such purposes have ordinarily an organic polymer layer for at least parts of an insulation layer thereof. The previous boards contains much pinholes and voids in the organic polymer layer, are different in the characteristics in a central area and a circumference of the organic polymer layer, and involve a problem of its adhesion with an undercoat film. Thus, the hitherto boards are low in the yield in its fabrication process and not sufficiently high in its wiring density.
The hitherto techniques are described below by reference to the accompanying drawings.
The following describes a method of fabricating a hitherto multilayer wiring board having a ceramic wiring board used as a base substrate by reference to process step chart in FIGS. 14a to 14g.
As shown in FIG. 14a, a substrate 1401 has a metallic undercoat layer 1402 formed for use as an electrode available for plating on an entire upper surface thereof. As shown in FIG. 14b, on the upper surface is formed a resist 1403 having grooves formed to a desired conductor pattern shape. After this, the metallic undercoat layer 1402 on exposed portions 1404 of the grooves is electroplated as a cathode. The groove portions 1404 of the resist 1403, as shown in FIG. 14c, are selectively filled with conductor to form conductors 1405 for wires, vias, grounds, and power supplies. In turn, as shown in FIG. 14d, the resist 1403 is removed to expose the conductors 1405. Then, as shown in FIG. 14e, the metallic undercoat layer 1402 other than the portions contacting the conductor 1405 is removed. In turn, as shown in FIG. 14f, a polymer insulation layer 1406 is formed so as to enclose the conductor 1405 on the entire surface of the substrate 1401. Then, as shown in FIG. 14g, an upper surface of the conductor 1405 is exposed by grinding or a similar process and at the same time, a surface of the insulation layer 1406 is polished. The process steps described above are repeated a few times as necessary to fabricate the multilayer wiring board. The above-described technique for forming the conductor pattern was disclosed in the Japanese Patent Application Laid-Open Nos. 57-50489, 57-50490, and 57-50491. The above-described technique for forming the insulation layer was disclosed in the Japanese Patent Application Laid-Open No. 50-64767.
Also, the following describes a method of fabricating another hitherto multilayer wiring board by reference to process step chart in FIGS. 15a to 15g.
As shown in FIGS. 15a and 15b, a substrate 1501 has a first conductor layer 1502 and a second conductor layer 1503 as a contact post formed thereon. These layers have an epoxy resin or polyimide 1504 in a B-stage stuck on surfaces thereof as shown in FIG. 15c. In turn, as shown in FIG. 15d, these resin layers are hardened while being vertically pressed to form a planar insulation layer 1506 having the surface 1505 exposed as the contact post. In turn, as shown in FIG. 15c, a third conductor layer 1507 is formed in connection with the contact post exposed on the insulation layer to form the multilayer wiring board. The above-described technique for forming the multilayer wiring board the conductor pattern was disclosed in the Japanese Patent Publication Nos. 4-38157 and 4-38158.
Note that in general, the metallic undercoat which is necessary for forming the wiring layers is formed in a dry filming method, such as the sputtering process or evaporation process, as in described in the Japanese Patent Application Laid-Open Nos. 57-50489, 57-50490, and 57-50491.
Further, there is a known method of fabricating still another previous multilayer wiring board with a photosensitive insulating material, such as a photosensitive polyimide, in a simpler process than the above-described two hitherto techniques, although a diameter of a via is generally larger. An example was disclosed in the Japanese Patent Publication No. 62-43544.
On the other hand, the following describes an example of structure of a hitherto multilayer wiring board having a printed wiring board used as a base substrate by reference to FIG. 16.
A method of fabricating this multilayer wiring board is based on a way similar to the hitherto one of fabricating the multilayer wiring board having the photosensitive polyimide used therein. The board, however, can be made to have a higher density than the hitherto one having plated through-holes used to make inter-layer connections. The method of fabricating the multilayer wiring board basically includes a process that the printed wiring board having a patterning made on a surface conductor thereof is treated to have a photosensitive insulating material filmed on a surface layer thereof. Via holes are formed by exposure and development. In turn, a conductor is formed on an entire surface before being patterned. Further, the process is repeated to form a multilayer. Finally, plated through-holes are formed. The above-described method of fabricating the multilayer wiring board is called the build-up process. In this method, as shown in FIG. 16, connections of a printed wiring board surface-layer conductor 1600 with a build-up conductor layer 1601 and of the build-up conductor layers together are not made by a plated through-hole 1602 through drilling, but by a conformal via 1603. The multilayer wiring board, thus, can be made denser than the printed wiring board having the surface-layer connection made only by the usual plated through-hole. Forming the metallic undercoat needed for forming the wiring layers is usually made by electroless plating. An example of the build-up process is given in the Japanese Patent Application Laid-Open No. 4-148590.
Further, as shown in FIG. 17, the Japanese Patent Application Laid-Open No. 4-168794 disclosed an example of method of fabricating a multilayer printed wiring board which can effectively use areas of plated through-holes in the way that plated through-holes formed for inter-layer connections by drilling are filled with a resin before conductor pads to be connected with the plated through-holes are formed on their tops.
In FIG. 17 are indicated a printed wiring board 1701, conductor layers 1702, 1703, 1704, and 1705, and the plated through-hole 1706.
A first difficult problem of the previous techniques is in a insulation film forming step and a planarization step.
In the insulation film forming step shown in FIG. 14f and the planarization step in FIG. 14g, a polyimide usually used as the polymer for forming the insulation layer 1406 tends to have pinholes and voids as its solvent and moisture are evaporated by a thermal hardening reaction. The polyimide shrinks along irregularity of the undercoat, the insulation film is formed along the irregularity of the substrate, resulting in adversely deficient planarization. Therefore, the soft polyimide and the hard metallic conductor have to be ground and polished to make a sufficient planarization. This process takes a long time. Also, it is not easy to remove the foreign matters of ground powder and polished powder through cleaning. Further, as the polyimide insulation film is obtained from polyamic acid solution or polyimide solution by being coated and heated, a required film thickness cannot be obtained at a time. More times of coatings and heatings have to be made. Still further, hardening the polyimide takes a high temperature and a long time. With such a number of problems, this hitherto method of fabricating the multilayer wiring board is defective in low yield, many number of process steps, long lead time, and very low mass productivity.
In the hitherto technique shown in FIGS. 15a to 15e, the polyamic acid solution or the epoxy resin solution in FIG. 15c is coated before the solvent is vaporized to stick the epoxy resin or polyamic acid to the wiring layer. Vaporization of the remaining solvent in hardening, then, causes voids and pinholes. Also, vaporization of the condensed water due to hardening of the polyamic acid causes voids and pinholes. Further, even if coating is made without solvent, air is involved in between the wiring layers 1502 and 1503 and the insulation layer 1504, causing gaps and bubbles to remain. These also cause voids and pinholes. These defects in the insulation film do not only make it difficult to form the upper wiring layer, but also fetches into the insulation film the process solution in the wet process in plating and etching for forming the wiring. This causes insulation failure. To proceed with hitherto technique shown in FIGS. 15a to 15e, we must use epoxy resin without solvent or a polyimide resin without solvent which is very low in viscosity. If such a material is used, however, the wiring is strongly pressed to the mold, causing wiring deformation and breaking. If the viscosity is made higher, the resin cannot only be filled in between the wirings, but also the wiring has a thick resin remained on the upper surface thereof. In addition, as the pressure is only compression, it is not uniformly applied to the resin. This results in that a central portion of the insulation layer having higher pressure and a circumferential portion of the insulation layer having lower pressure have different in the physical properties, including the heat resistance, the thermal expansion coefficient, and the mechanical strength. Also, the resin leaks off the substrate. Further, a film thickness of the circumferential portion of the insulation layer is made thinner. Still further, the air involved in the leaking, the air dissolved in the resin, and the evaporation of moisture cause voids and pinholes on the circumferential portion of the insulation layer. Still further, the mere compressing pressure causes remaining of thin film of around 1 .mu.m thick on the upper surface of the wiring. The remaining thin film cannot be ignored. With such many problems, this hitherto method of fabricating the multilayer wiring board is defective in low yield.
A second difficult problem of the hitherto techniques is in a adhesive strength of the wiring conductor with the insulation film in forming the next wiring layer after the insulation film was formed. In general, forming a conductive undercoat film for electroless plating or electroplating is made in a dry filming method, such as the sputtering process or evaporation process, as in described in the Japanese Patent Application Laid-Open Nos. 57-50489, 57-50490, and 57-50491. The sputtering process provides a relatively high adhesive strength as the conductive undercoat film is physically dug in the insulation film. On the other hand, as the evaporation process does not have such an effect, its adhesive strength is inferior to that of the sputtering process. However, as the sputtering process and the evaporation process need expensive apparatuses and take a long filming time, they cannot be said as low-cost, high-through-put processes. An electroless plating process is often used in fabrication of the printed wiring board. In the electroless plating process, the surface of the insulation film is subjected to etching to have an irregularity depending on the intensity of the etching. An adhesive strength of the insulation film with the conductive undercoat film is maintained by an anchor effect of the irregularity. The electroless plating process provides a relatively high adhesive strength. However, composition of the insulating material has to be highly elaborated to make the etching contrast. That is, the composition has to contain a constituent which is likely etched and a constituent which is hard to etch. It therefore is in a trade-off relationship with the physical properties, such as the heat resistance and the mechanical properties. Also, it is hard to stably form a constant rough surface and thus difficult to stably maintain the adhesive strength.
On the other hand, the build-up process for the printed wiring board has a diameter of a bottom of the conformal via 1603 limited to 100 .mu.m in view of a resolution of the photosensitive insulating material, such as a photosensitive epoxy material. To prevent the conductor from breaking down, further, the conformal via has to be shaped to taper. Thus, the surface area occupied by the via including the land is too wide to made the via diameter narrower to make the density higher. As the conformal via has an irregularity formed on the upper surface thereof, also, the next conformal via or wiring conductor cannot be formed on that. This means that vias at two positions are used for connection of separated thin-film multilayer wiring layers. This results in that the number of vias is lost. Also, a thermal via which is a heat conductor via for heat radiation cannot be formed. Further, the conductor has to have a wider cross-section because of its wiring resistance. Forming a square pattern of a thick conductor is superior to form a finer pattern to forming a rectangular pattern of a thin conductor. Notwithstanding, if the conductor is made thick to make patterning by etching after the conductor is formed, the finer wiring pattern cannot be formed. On the other hand, as the connection with the inner conductor layer of the printed wiring board or the connection of the both surfaces of the printed wiring board is made with the plated through-hole 1602 formed at the final stage. This is defective because the plated through-hole decreases the wiring density. Also, the printed wiring board having the plated through-hole formed by drilling and non-filled cannot have a liquid-like material, such as the photosensitive insulation material or resist, formed to film. The build-up process, therefore, cannot form the thin-film multilayer wiring layers. Further, as shown in FIG. 17, in the Japanese Patent Application Laid-Open No. 4-168794 can effectively use the areas of plated through-holes in the way that the plated through-holes formed for the inter-layer connections by drilling are filled with the resin before the conductor pads to be connected with the plated through-holes are formed on their tops. The laid-open is effective for connection of the two sets of the adjoining conductor layers 1702 and 1703, 1704 and 1705 of the multilayer printed wiring board. However, the connection of the both surfaces of the printed wiring layers or two separated conductor layers has to unavoidably depend on the plated through-hole 1706 formed at the final stage. The finished multilayer printed wiring board has the non-filled plated through-hole left thereon.
Note that a multilayer wiring board fabricating method with use of a fluid polymer precursor into is described to some extent in the U.S. patent application Ser. No. 07/672,117, filed Mar. 19, 1991, now abandoned, and its continuation-in-part application Ser. No. 08/037,543, file Mar. 22, 1993, now U.S. Pat. No. 5,300,735, both of which have not been issued at present.